This disclosure relates to methods for increasing the current carrying capacity of a semiconductor component and to semiconductor components with increased current carrying capacity.
High power semiconductor components such as diodes and transistors, e.g., MOS-FETs and IGBTs, are normally provided to the customer as a packaged semiconductor component. The packaged semiconductor component, typically, has one of a number of standard package outlines which conforms to agreed industry standards regarding the outer form and dimensions of the plastic package as well as the number, dimensions and spacing of the pins. A standard package outline has the advantage that the component can be simply mounted on standardized printed circuit boards.
However, the packages suffer from the disadvantage that the current carrying capacity is limited. In order to increase the current carrying capacity, it is known, for example from US 2003/0011051, to provide two or more bonding wires which are connected in parallel between the power electrode of the semiconductor die and the source lead of the lead-frame.
The leadframe and package outline are also modified in order to further increase the current carrying capacity. The pin sequence of the package is changed in order to increase the size of the source post, or inner contact area of the source pin. Additionally, the cross-sectional area of the external portions of the pins is increased to increase the current carrying capacity of the package.
However, although the current carrying capacity may be increased by modifying the package and pins, the advantages offered to the user of a standard package outline and a standard pin arrangement are lost. The user, therefore, has to modify the board in order to be able to mount the modified package. This increases the complexity for the user and increases the costs which can outweigh the benefit of a higher current carrying capacity.
For these and other reasons, there is a need for the present invention.